#pragma once
#define uint32_t unsigned long

#define __IO volatile

#define SF32LB52X 1

/* --------  Configuration of Core Peripherals  ----------------------------------- */
#define __CM33_REV                0x0000U   /* Core revision r0p1 */
#define __SAUREGION_PRESENT       0U        /* SAU regions present */
#define __MPU_PRESENT             1U        /* MPU present */
#define __VTOR_PRESENT            1U        /* VTOR present */
#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
#ifndef __FPU_PRESENT
#define __FPU_PRESENT             1U        /* no FPU present */
#endif /* __FPU_PRESENT */
#ifndef __DSP_PRESENT
#define __DSP_PRESENT             1U        /* no DSP extension present */
#endif

/******************* Base Addresss Definition ******************/
//================== MCU_HPSYS ===================
#define HPSYS_RCC_BASE      0x50000000
#define EXTDMA_BASE         0x50001000
#define SECU1_BASE          0x50002000
#define PINMUX1_BASE        0x50003000
#define ATIM1_BASE          0x50004000
#define AUDPRC_BASE         0x50005000
#define EZIP1_BASE          0x50006000
#define EPIC_BASE           0x50007000
#define LCDC1_BASE          0x50008000
#define I2S1_BASE           0x50009000
#define HPSYS_CFG_BASE      0x5000b000
#define EFUSEC_BASE         0x5000c000
#define AES_BASE            0x5000d000
#define TRNG_BASE           0x5000f000
//------------------------------------
#define MPI1_BASE           0x50041000
#define MPI2_BASE           0x50042000
#define SDMMC1_BASE         0x50045000
#define USBC_BASE           0x50047000
#define CRC1_BASE           0x50048000
#define EPIC_RAM_BASE       0x50050000
//------------------------------------
#define PTC1_BASE           0x50080000
#define DMAC1_BASE          0x50081000
#define MAILBOX1_BASE       0x50082000
#define USART1_BASE         0x50084000
#define USART2_BASE         0x50085000
#define USART3_BASE         0x50086000
#define GPADC_BASE          0x50087000
#define AUDCODEC_BASE       0x50088000
#define TSEN_BASE           0x50089000
#define GPTIM1_BASE         0x50090000
#define BTIM1_BASE          0x50092000
#define WDT1_BASE           0x50094000
#define SPI1_BASE           0x50095000
#define SPI2_BASE           0x50096000
#define PDM1_BASE           0x5009a000
#define I2C1_BASE           0x5009c000
#define I2C2_BASE           0x5009d000
#define I2C3_BASE           0x5009e000
#define I2C4_BASE           0x5009f000
//------------------------------------
#define GPIO1_BASE          0x500a0000
//------------------------------------
#define GPTIM2_BASE         0x500b0000
#define BTIM2_BASE          0x500b1000
//------------------------------------
#define HPSYS_AON_BASE      0x500c0000
#define LPTIM1_BASE         0x500c1000
#define LPTIM2_BASE         0x500c2000
#define PMUC_BASE           0x500ca000
#define RTC_BASE            0x500cb000
#define IWDT_BASE           0x500cc000
//TODO PMIC

//================== MCU_LPSYS ===================
#define LPSYS_RCC_BASE      0x40000000
#define DMAC2_BASE          0x40001000
#define MAILBOX2_BASE       0x40002000
#define PINMUX2_BASE        0x40003000
#define PATCH_BASE          0x40004000
#define USART4_BASE         0x40005000
#define USART5_BASE         0x40006000
#define SECU2_BASE          0x40007000
#define BTIM3_BASE          0x40009000
#define BTIM4_BASE          0x4000a000
#define WDT2_BASE           0x4000b000
#define PTC2_BASE           0x4000c000
#define LPSYS_CFG_BASE      0x4000f000
//------------------------------------
#define LPSYS_AON_BASE      0x40040000
#define LPTIM3_BASE         0x40042000
//------------------------------------
#define GPIO2_BASE          0x40080000
#define BT_RFC_MEM_BASE     0x40082000
#define BT_RFC_REG_BASE     0x40082800
#define BT_PHY_BASE         0x40084000
#define CRC2_BASE           0x40085000
#define BT_MAC_BASE         0x40090000




typedef enum IRQn
{
    /* -------------------  Processor Exceptions Numbers  ----------------------------- */
    NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */
    HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */
    MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */
    BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */
    UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */
    SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */
    SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */
    DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */
    PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */
    SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */

    /* -------------------  Processor Interrupt Numbers  ------------------------------ */
    AON_IRQn                      =   0,
    BLE_MAC_IRQn                  =   1,
    DMAC2_CH1_IRQn                =   2,
    DMAC2_CH2_IRQn                =   3,
    DMAC2_CH3_IRQn                =   4,
    DMAC2_CH4_IRQn                =   5,
    DMAC2_CH5_IRQn                =   6,
    DMAC2_CH6_IRQn                =   7,
    DMAC2_CH7_IRQn                =   8,
    DMAC2_CH8_IRQn                =   9,
    PATCH_IRQn                    =  10,
    DM_MAC_IRQn                   =  11,
    USART4_IRQn                   =  12,
    USART5_IRQn                   =  13,
    SECU2_IRQn                    =  14,
    BT_MAC_IRQn                   =  15,
    BTIM3_IRQn                    =  16,
    BTIM4_IRQn                    =  17,
    PTC2_IRQn                     =  18,
    LPTIM3_IRQn                   =  19,
    GPIO2_IRQn                    =  20,
    HPSYS0_IRQn                   =  21,
    HPSYS1_IRQn                   =  22,
    Interrupt23_IRQn              =  23,
    Interrupt24_IRQn              =  24,
    Interrupt25_IRQn              =  25,
    Interrupt26_IRQn              =  26,
    Interrupt27_IRQn              =  27,
    Interrupt28_IRQn              =  28,
    Interrupt29_IRQn              =  29,
    Interrupt30_IRQn              =  30,
    Interrupt31_IRQn              =  31,
    Interrupt32_IRQn              =  32,
    Interrupt33_IRQn              =  33,
    Interrupt34_IRQn              =  34,
    Interrupt35_IRQn              =  35,
    Interrupt36_IRQn              =  36,
    Interrupt37_IRQn              =  37,
    Interrupt38_IRQn              =  38,
    Interrupt39_IRQn              =  39,
    Interrupt40_IRQn              =  40,
    Interrupt41_IRQn              =  41,
    Interrupt42_IRQn              =  42,
    Interrupt43_IRQn              =  43,
    Interrupt44_IRQn              =  44,
    Interrupt45_IRQn              =  45,
    LPTIM1_IRQn                   =  46,
    LPTIM2_IRQn                   =  47,
    PMUC_IRQn                     =  48,
    RTC_IRQn                      =  49,
    DMAC1_CH1_IRQn                =  50,
    DMAC1_CH2_IRQn                =  51,
    DMAC1_CH3_IRQn                =  52,
    DMAC1_CH4_IRQn                =  53,
    DMAC1_CH5_IRQn                =  54,
    DMAC1_CH6_IRQn                =  55,
    DMAC1_CH7_IRQn                =  56,
    DMAC1_CH8_IRQn                =  57,
    LCPU2HCPU_IRQn                =  58,
    USART1_IRQn                   =  59,
    SPI1_IRQn                     =  60,
    I2C1_IRQn                     =  61,
    EPIC_IRQn                     =  62,
    LCDC1_IRQn                    =  63,
    I2S1_IRQn                     =  64,
    GPADC_IRQn                    =  65,
    EFUSEC_IRQn                   =  66,
    AES_IRQn                      =  67,
    PTC1_IRQn                     =  68,
    TRNG_IRQn                     =  69,
    GPTIM1_IRQn                   =  70,
    GPTIM2_IRQn                   =  71,
    BTIM1_IRQn                    =  72,
    BTIM2_IRQn                    =  73,
    USART2_IRQn                   =  74,
    SPI2_IRQn                     =  75,
    I2C2_IRQn                     =  76,
    EXTDMA_IRQn                   =  77,
    I2C4_IRQn                     =  78,
    SDMMC1_IRQn                   =  79,
    Interrupt80_IRQn              =  80,
    Interrupt81_IRQn              =  81,
    PDM1_IRQn                     =  82,
    Interrupt83_IRQn              =  83,
    GPIO1_IRQn                    =  84,
    MPI1_IRQn                     =  85,
    MPI2_IRQn                     =  86,
    Interrupt87_IRQn              =  87,
    Interrupt88_IRQn              =  88,
    EZIP_IRQn                     =  89,
    AUDPRC_IRQn                   =  90,
    TSEN_IRQn                     =  91,
    USBC_IRQn                     =  92,
    I2C3_IRQn                     =  93,
    ATIM1_IRQn                    =  94,
    USART3_IRQn                   =  95,
    AUD_HP_IRQn                   =  96,
    Interrupt97_IRQn              =  97,
    SECU1_IRQn                    =  98,
    HCPU2LCPU_IRQn                =  -1,
    /* Interrupts 99 .. 479 are left out */
} IRQn_Type;
 

typedef struct
{
    __IO uint32_t RSTR1;
    __IO uint32_t RSTR2;
    __IO uint32_t ENR1;
    __IO uint32_t ENR2;
    __IO uint32_t ESR1;
    __IO uint32_t ESR2;
    __IO uint32_t ECR1;
    __IO uint32_t ECR2;
    __IO uint32_t CSR;
    __IO uint32_t CFGR;
    __IO uint32_t USBCR;
    __IO uint32_t DLL1CR;
    __IO uint32_t DLL2CR;
    __IO uint32_t HRCCAL1;
    __IO uint32_t HRCCAL2;
    __IO uint32_t DBGCLKR;
    __IO uint32_t DBGR;
    __IO uint32_t DWCFGR;
    __IO uint32_t RSVD1[13];
    __IO uint32_t TESTR;
} HPSYS_RCC_TypeDef;

typedef struct
{
    __IO uint32_t CR1;
    __IO uint32_t CR2;
    __IO uint32_t CR3;
    __IO uint32_t BRR;
    __IO uint32_t GTPR;
    __IO uint32_t RTOR;
    __IO uint32_t RQR;
    __IO uint32_t ISR;
    __IO uint32_t ICR;
    __IO uint32_t RDR;
    __IO uint32_t TDR;
    __IO uint32_t MISCR;
#if defined(SF32LB56X)|| defined(SF32LB52X)
    __IO uint32_t DRDR;
    __IO uint32_t DTDR;
    __IO uint32_t EXR;
#endif /* SF32LB56X */
} USART_TypeDef;

typedef struct
{
    __IO uint32_t DIR;
    __IO uint32_t DOR;
#ifndef SF32LB55X
    __IO uint32_t DOSR;
    __IO uint32_t DOCR;
#endif
    __IO uint32_t DOER;
    __IO uint32_t DOESR;
    __IO uint32_t DOECR;
    __IO uint32_t IER;
    __IO uint32_t IESR;
    __IO uint32_t IECR;
    __IO uint32_t ITR;
    __IO uint32_t ITSR;
    __IO uint32_t ITCR;
#ifndef SF32LB55X
    __IO uint32_t IPHR;
    __IO uint32_t IPHSR;
    __IO uint32_t IPHCR;
    __IO uint32_t IPLR;
    __IO uint32_t IPLSR;
    __IO uint32_t IPLCR;
#else
    __IO uint32_t IPSR;
    __IO uint32_t IPCR;
#endif
    __IO uint32_t ISR;
#ifndef SF32LB55X
    __IO uint32_t IER_EXT;
    __IO uint32_t IESR_EXT;
    __IO uint32_t IECR_EXT;
    __IO uint32_t ISR_EXT;
    __IO uint32_t OEMR;
    __IO uint32_t OEMSR;
    __IO uint32_t OEMCR;
    __IO uint32_t RSVD2[5];
#endif
} GPIO_TypeDef;


typedef struct
{
    __IO uint32_t PAD_SA00;
    __IO uint32_t PAD_SA01;
    __IO uint32_t PAD_SA02;
    __IO uint32_t PAD_SA03;
    __IO uint32_t PAD_SA04;
    __IO uint32_t PAD_SA05;
    __IO uint32_t PAD_SA06;
    __IO uint32_t PAD_SA07;
    __IO uint32_t PAD_SA08;
    __IO uint32_t PAD_SA09;
    __IO uint32_t PAD_SA10;
    __IO uint32_t PAD_SA11;
    __IO uint32_t PAD_SA12;
    __IO uint32_t PAD_PA00;
    __IO uint32_t PAD_PA01;
    __IO uint32_t PAD_PA02;
    __IO uint32_t PAD_PA03;
    __IO uint32_t PAD_PA04;
    __IO uint32_t PAD_PA05;
    __IO uint32_t PAD_PA06;
    __IO uint32_t PAD_PA07;
    __IO uint32_t PAD_PA08;
    __IO uint32_t PAD_PA09;
    __IO uint32_t PAD_PA10;
    __IO uint32_t PAD_PA11;
    __IO uint32_t PAD_PA12;
    __IO uint32_t PAD_PA13;
    __IO uint32_t PAD_PA14;
    __IO uint32_t PAD_PA15;
    __IO uint32_t PAD_PA16;
    __IO uint32_t PAD_PA17;
    __IO uint32_t PAD_PA18;
    __IO uint32_t PAD_PA19;
    __IO uint32_t PAD_PA20;
    __IO uint32_t PAD_PA21;
    __IO uint32_t PAD_PA22;
    __IO uint32_t PAD_PA23;
    __IO uint32_t PAD_PA24;
    __IO uint32_t PAD_PA25;
    __IO uint32_t PAD_PA26;
    __IO uint32_t PAD_PA27;
    __IO uint32_t PAD_PA28;
    __IO uint32_t PAD_PA29;
    __IO uint32_t PAD_PA30;
    __IO uint32_t PAD_PA31;
    __IO uint32_t PAD_PA32;
    __IO uint32_t PAD_PA33;
    __IO uint32_t PAD_PA34;
    __IO uint32_t PAD_PA35;
    __IO uint32_t PAD_PA36;
    __IO uint32_t PAD_PA37;
    __IO uint32_t PAD_PA38;
    __IO uint32_t PAD_PA39;
    __IO uint32_t PAD_PA40;
    __IO uint32_t PAD_PA41;
    __IO uint32_t PAD_PA42;
    __IO uint32_t PAD_PA43;
    __IO uint32_t PAD_PA44;
} HPSYS_PINMUX_TypeDef;
typedef struct
{
    __IO uint32_t BMR;
    __IO uint32_t IDR;
    __IO uint32_t SWCR;
    __IO uint32_t SCR;
    __IO uint32_t SYSCR;
    __IO uint32_t RTC_TR;
    __IO uint32_t RTC_DR;
    __IO uint32_t ULPMCR;
    __IO uint32_t DBGR;
    __IO uint32_t MDBGR;
    __IO uint32_t BISTCR;
    __IO uint32_t BISTR;
    __IO uint32_t ROMCR0;
    __IO uint32_t ROMCR1;
    __IO uint32_t ROMCR2;
    __IO uint32_t LPIRQ;
    __IO uint32_t USBCR;
    __IO uint32_t SYS_RSVD;
    __IO uint32_t I2C1_PINR;
    __IO uint32_t I2C2_PINR;
    __IO uint32_t I2C3_PINR;
    __IO uint32_t I2C4_PINR;
    __IO uint32_t USART1_PINR;
    __IO uint32_t USART2_PINR;
    __IO uint32_t USART3_PINR;
    __IO uint32_t GPTIM1_PINR;
    __IO uint32_t GPTIM2_PINR;
    __IO uint32_t ETR_PINR;
    __IO uint32_t LPTIM1_PINR;
    __IO uint32_t LPTIM2_PINR;
    __IO uint32_t ATIM1_PINR1;
    __IO uint32_t ATIM1_PINR2;
    __IO uint32_t ATIM1_PINR3;
    __IO uint32_t PTA_PINR;
    __IO uint32_t ANAU_CR;
    __IO uint32_t ANAU_RSVD;
    __IO uint32_t ANATR;
    __IO uint32_t CAU2_CR;
    __IO uint32_t CAU2_RSVD;
} HPSYS_CFG_TypeDef;

#define hwp_hpsys_rcc   ((HPSYS_RCC_TypeDef     *)    HPSYS_RCC_BASE)
#define hwp_usart1      ((USART_TypeDef         *)    USART1_BASE)
#define hwp_usart2      ((USART_TypeDef         *)    USART2_BASE)
#define hwp_usart3      ((USART_TypeDef         *)    USART3_BASE)
#define hwp_usart4      ((USART_TypeDef         *)    USART4_BASE)
#define hwp_usart5      ((USART_TypeDef         *)    USART5_BASE)
#define hwp_gpio1       ((GPIO_TypeDef         *)     GPIO1_BASE)
#define hwp_gpio2       ((GPIO_TypeDef         *)     GPIO2_BASE)
#define hwp_pinmux1     ((HPSYS_PINMUX_TypeDef  *)    PINMUX1_BASE)
#define hwp_hpsys_cfg   ((HPSYS_CFG_TypeDef     *)    HPSYS_CFG_BASE) 

#define USART1        hwp_usart1
#define USART2        hwp_usart2
#define USART3        hwp_usart3
#define USART4        hwp_usart4
#define USART5        hwp_usart5

#if !defined(UNUSED)
#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
#endif /* UNUSED */

#define SET_BIT(REG, BIT)     ((REG) |= (BIT))

#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))

#define READ_BIT(REG, BIT)    ((REG) & (BIT))

#define CLEAR_REG(REG)        ((REG) = (0x0))

#define WRITE_REG(REG, VAL)   ((REG) = (VAL))

#define READ_REG(REG)         ((REG))


/* bit operations */
#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x)                       ((uint32_t)((uint32_t)0x01U<<(x)))
#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
 

#define SET_REG_BIT(ADDR,BIT) (*(volatile uint32_t *)(ADDR)|=  (BIT))
#define CLEAR_REG_BIT(ADDR,BIT) (*(volatile uint32_t *)(ADDR)&= ~ (BIT))
 